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2010
IEEE
139views Hardware» more  DATE 2010»
15 years 4 months ago
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
Jun Zhu, Ingo Sander, Axel Jantsch
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
15 years 4 months ago
Verifying UML/OCL models using Boolean satisfiability
Abstract--Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesig...
Mathias Soeken, Robert Wille, Mirco Kuhlmann, Mart...
DATE
2010
IEEE
122views Hardware» more  DATE 2010»
15 years 4 months ago
Optimal regulation of traffic flows in networks-on-chip
We have proposed (, )-based flow regulation to reduce delay and backlog bounds in SoC architectures, where bounds the traffic burstiness and the traffic rate. The regulation is co...
Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohamma...
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
15 years 18 hour ago
Automatic pipelining from transactional datapath specifications
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-...
DATE
2010
IEEE
132views Hardware» more  DATE 2010»
14 years 10 months ago
Differential Power Analysis enhancement with statistical preprocessing
—Differential Power Analysis (DPA) is a powerful Side-Channel Attack (SCA) targeting as well symmetric as asymmetric ciphers. Its principle is based on a statistical treatment of...
Victor Lomné, Amine Dehbaoui, Philippe Maur...