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2010
IEEE
180views Hardware» more  DATE 2010»
15 years 5 months ago
A reconfigurable cache memory with heterogeneous banks
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
Domingo Benitez, Juan C. Moure, Dolores Rexachs, E...
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
15 years 4 months ago
Efficient High-Level modeling in the networking domain
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
Christian Zebelein, Joachim Falk, Christian Haubel...
DATE
2010
IEEE
130views Hardware» more  DATE 2010»
15 years 3 months ago
Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller
Abstract—Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips for the sake of reusing huge amount of legacy code and easy programmability. We p...
Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming C...
DATE
2010
IEEE
183views Hardware» more  DATE 2010»
14 years 10 months ago
Toward optimized code generation through model-based optimization
—Model-Based Development (MBD) provides an al level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic tr...
Asma Charfi, Chokri Mraidha, Sébastien G&ea...
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 5 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...