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2010
IEEE
163views Hardware» more  DATE 2010»
15 years 4 months ago
A methodology for the characterization of process variation in NoC links
—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that...
Carles Hernandez, Federico Silla, José Duat...
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
15 years 4 months ago
Optimizing equivalence checking for behavioral synthesis
Abstract—Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checki...
Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang
DATE
2010
IEEE
176views Hardware» more  DATE 2010»
15 years 4 months ago
Timing modeling and analysis for AUTOSAR-based software development - a case study
—Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSARbased l...
Kay Klobedanz, Christoph Kuznik, Andreas Thuy, Wol...
DATE
2010
IEEE
76views Hardware» more  DATE 2010»
15 years 4 months ago
Scalable codeword generation for coupled buses
—Inductive and capacitive coupling are responsible for slowing down signals. Existing bus encoding techniques tackle the issue by avoiding certain types of transitions. This work...
Kedar Karmarkar, Spyros Tragoudas
DATE
2010
IEEE
104views Hardware» more  DATE 2010»
15 years 4 months ago
Large-scale Boolean matching
— We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking problem) — a key step in incremental logic design that identif...
Hadi Katebi, Igor L. Markov