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DFT
1994
IEEE
157views VLSI» more  DFT 1994»
15 years 10 months ago
An Approach to the Development of a IDDQ Testable Cell Library
C. Ferrer, D. Dateo, J. Oliver, Antonio Rubio, M. ...
EURODAC
1994
IEEE
94views VHDL» more  EURODAC 1994»
15 years 10 months ago
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT
Undetectable shorts may decrease the long term reliability of a circuit, cause intermittent failures, add noise and delay, or increase test pattern generation costs. This paper de...
Richard McGowen, F. Joel Ferguson
DAC
1994
ACM
15 years 10 months ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
DFT
1994
IEEE
121views VLSI» more  DFT 1994»
15 years 10 months ago
Reconfiguration in 3D Meshes
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
Anuj Chandra, Rami G. Melhem