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DSD
2002
IEEE
88views Hardware» more  DSD 2002»
13 years 11 months ago
The Synthesis of a Hardware Scheduler for Non-Manifest Loops
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
Omar Mansour, Egbert Molenkamp, Thijs Krol
DSD
2002
IEEE
90views Hardware» more  DSD 2002»
13 years 11 months ago
Simplifying Instruction Issue Logic in Superscalar Processors
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
Toshinori Sato, Itsujiro Arita
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
13 years 11 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...
DSD
2002
IEEE
73views Hardware» more  DSD 2002»
13 years 11 months ago
Implementation of a Streaming Execution Unit
The Complex Streamed Instruction (CSI) set is an instruction set extension targeted at multimedia applications. CSI instructions process two-dimensional data streams stored in mem...
Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vass...
DSD
2002
IEEE
103views Hardware» more  DSD 2002»
13 years 11 months ago
On the Fundamental Design Gap in Terabit per Second Packet Switching
We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced ...
M. Verhappen, P. H. A. van der Putten, Jeroen Voet...