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DSD
2008
IEEE
110views Hardware» more  DSD 2008»
14 years 11 months ago
VLSI Implementation of a Cryptography-Oriented Reconfigurable Array
The long-word and very long-word addition required in cryptography applications generally requires custom hardware support provided by ASICs or application-specific instructions i...
Scott Miller, Ambrose Chu, Mihai Sima, Michael McG...
DSD
2008
IEEE
168views Hardware» more  DSD 2008»
14 years 11 months ago
Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture
In this paper we present results of parallelization of Deblocking Filter (DF) of H.264 video codec on Decoupled Threaded Architecture (DTA). We parallelized the code trying to exp...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, A...
DSD
2008
IEEE
127views Hardware» more  DSD 2008»
15 years 4 months ago
Measurement, Analysis and Modeling of RTOS System Calls Timing
This paper presents a methodology for accurately characterizing the system calls of an operating system for embedded applications. Characterization consists of two phases: measure...
Carlo Brandolese, William Fornaciari
DSD
2008
IEEE
85views Hardware» more  DSD 2008»
15 years 4 months ago
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...
Josef Strnadel
DSD
2008
IEEE
108views Hardware» more  DSD 2008»
14 years 11 months ago
Reducing Leakage through Filter Cache
We evaluate the leakage reduction for both instruction and data cache in presence of drowsy or decay techniques. We discovered that a filter cache, traditionally used for reducing...
Roberto Giorgi, Paolo Bennati