34 search results - page 4 / 7 » ersa 2006 |
75
Voted
ERSA
2006
14 years 11 months ago
2006
This paper deals with the question of task communication and configuration dynamic management in the context of hardware and software implementations. Our approach is based on a c...
83
Voted
ERSA
2006
14 years 11 months ago
2006
We propose an improved implementation of the SHA-2 hash family to include a multi-mode of operation with minimal latency and hardware requirements over the entire operator. The mul...
83
Voted
ERSA
2006
14 years 11 months ago
2006
In this case study, various ways to partition a code between the microprocessor and FPGA are examined. Discrete image convolution operation with separable kernel is used as the ca...
ERSA
2006
14 years 11 months ago
2006
Current FPGAs are heterogeneous partially reconfigurable architectures, consisting of several resource types, e. g., logic cells and embedded memory. By using partial reconfigurat...
ERSA
2006
14 years 11 months ago
2006
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...