34 search results - page 6 / 7 » ersa 2006 |
80
Voted
ERSA
2006
14 years 11 months ago
2006
- This paper presents the design and implementation methodology of some low power programmable FIR filtering IP cores targeting SoRC and compares their performance in term of area,...
103
Voted
ERSA
2006
14 years 11 months ago
2006
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
81
Voted
ERSA
2006
14 years 11 months ago
2006
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
73
Voted
ERSA
2006
14 years 11 months ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
80
Voted
ERSA
2006
14 years 11 months ago
2006
Acoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo controller is its capability to hand...