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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
15 years 1 months ago
A process algebra interpretation of a verification oriented overlanguage of VHDL
The VOVHDL language was defined as a verification oriented VHDL
Catherine Bayol, Bernard Soulas, Dominique Borrion...
EURODAC
1994
IEEE
163views VHDL» more  EURODAC 1994»
15 years 1 months ago
VHDL and cyclic corrector codes
Cyclic corrector codes, or "block codes", are often used in telecommunications systems. To facilitate the design of coding/decoding circuits using this type of code, we ...
France Mendez
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
15 years 1 months ago
Modeling shared variables in VHDL
A set of concurrent processes communicating through shared variables is an often used model for hardware systems. This paper presents three modeling techniques for representing su...
Jan Madsen, Jens P. Brage
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 1 months ago
A portable and extendible testbed for distributed logic simulation
A exible test environment is presented that allows for dierent methods of parallelizing discrete event simulation to be evaluated in a uniform environment. The testbed is portabl...
Peter Luksch
EURODAC
1994
IEEE
112views VHDL» more  EURODAC 1994»
15 years 1 months ago
The use of semantic information for control of a complex routing tool
To handle increasingly complex design data, CAD tools are becoming more specialised and complex and hence, more difficult to use. This paper describes an interactive system that h...
Michael Brown, Nick Filer, Zahir Moosa