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EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 1 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
15 years 1 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 1 months ago
Design automation of self checking circuits
In this paper we explain the steps of the CAD tools developed for self checking circuits. The CAD tools developed are used to design Strongly Fault Secure, Strongly Code Disjoint ...
Sayed Mohammad Kia, Sri Parameswaran
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
15 years 1 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
15 years 1 months ago
Synthesis of Self-Testable Controllers
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
Sybille Hellebrand, Hans-Joachim Wunderlich