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fccm 2004
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A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
15 years 6 months ago
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www.emsec.ee.ucla.edu
Alireza Hodjat, Ingrid Verbauwhede
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Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays
15 years 6 months ago
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www.see.ed.ac.uk
Sami Khawam, Tughrul Arslan, Fred Westall
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Hardware-in-the-Loop Evolution of a 3-bit Multiplier
15 years 6 months ago
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ti.arc.nasa.gov
Gregory V. Larchev, Jason D. Lohn
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ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
15 years 6 months ago
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www.cercs.gatech.edu
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
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A Structured System Methodology for FPGA Based System-on-A-Chip Design
15 years 6 months ago
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cas.ee.ic.ac.uk
N. Pete Sedcole, Peter Y. K. Cheung, George A. Con...
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