This paper presents a code compression and on-thefly decompression scheme suitable for coarse-grain reconfigurable technologies. A novel unit-grouping dictionary based compression...
Nazish Aslam, Mark Milward, Ioannis Nousias, Tughr...
This paper presents the porting of an RTOS Micro C/OS-II on a novel reconfigurable instruction cell based architecture which fills the gap between DSP, FPGA and ASIC with high per...
Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arsla...
A technique is presented which allows an FPGAbased reconfigurable System-on-Chip to automatically and dynamically load hardware peripheral controllers and software device drivers ...
In this paper we present our work toward FPGA acceleration of phylogenetic reconstruction, a type of analysis that is commonly performed in the fields of systematic biology and co...
Abstract: FPGA-based acceleration of molecular dynamics (MD) has been the subject of several recent studies. Implementing long-range forces, however, has only recently been address...