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ICIP
2003
IEEE
15 years 11 months ago
Embedded co-processor architecture for CMOS based image acquisition
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the ful...
Julien Dubois, Marco Mattavelli
DAC
2003
ACM
15 years 10 months ago
Dynamic hardware/software partitioning: a first approach
Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy co...
Greg Stitt, Roman L. Lysecky, Frank Vahid
FCCM
2003
IEEE
113views VLSI» more  FCCM 2003»
15 years 2 months ago
Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development
Although domain-specialized FPGAs can offer significant area, speed and power improvements over conventional reconfigurable devices, there are several unique and unexplored design...
Kenneth Eguro, Scott Hauck
GLVLSI
2003
IEEE
202views VLSI» more  GLVLSI 2003»
15 years 2 months ago
System level design of real time face recognition architecture based on composite PCA
Design and implementation of a fast parallel architecture based on an improved principal component analysis (PCA) method called Composite PCA suitable for real-time face recogniti...
Rajkiran Gottumukkal, Vijayan K. Asari
ITC
2003
IEEE
149views Hardware» more  ITC 2003»
15 years 2 months ago
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study
Abstract: We discuss the development of Built-In SelfTest (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000...
Charles E. Stroud, Keshia N. Leach, Thomas A. Slau...