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ITC
2003
IEEE
162views Hardware» more  ITC 2003»
15 years 11 months ago
FPGA Interconnect Delay Fault Testing
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
Erik Chmelar
DAC
2003
ACM
16 years 7 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 11 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
CHES
2003
Springer
247views Cryptology» more  CHES 2003»
15 years 11 months ago
Very Compact FPGA Implementation of the AES Algorithm
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
Pawel Chodowiec, Kris Gaj
IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
15 years 11 months ago
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. N...