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ICANN
2005
Springer
15 years 7 months ago
A Real-Time, FPGA Based, Biologically Plausible Neural Network Processor
Abstract. A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project,...
Martin J. Pearson, Ian Gilhespy, Kevin N. Gurney, ...
DAC
2005
ACM
15 years 3 months ago
Matlab as a development environment for FPGA design
In this paper we discuss an efficient design flow from Matlab® to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algo...
Tejas M. Bhatt, Dennis McCain
95
Voted
DAC
2005
ACM
16 years 2 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
FPGA
2005
ACM
156views FPGA» more  FPGA 2005»
15 years 7 months ago
Design of programmable interconnect for sublithographic programmable logic arrays
Sublithographic Programmable Logic Arrays can be interconnected and restored using nanoscale wires. Building on a hybrid of bottom-up assembly techniques supported by conventional...
André DeHon
107
Voted
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 7 months ago
An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform
In this paper, the EX-VPR tool, which used for architecture level exploration, is presented. This tool belongs to an integrated framework (MEANDER) for mapping applications into a...
K. Siozios, Konstantinos Tatas, George Koutroumpez...