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DATE
2005
IEEE
116views Hardware» more  DATE 2005»
13 years 12 months ago
FPGA based Agile Algorithm-On-Demand Co-Processor
With growing computational needs of many real-world applications, frequently changing specifications of standards, and the high design and NRE costs of ASICs, an algorithm-agile ...
Ramachandran Pradeep, S. Vinay, Sanjay Burman, V. ...
FPGA
2005
ACM
137views FPGA» more  FPGA 2005»
13 years 11 months ago
HARP: hard-wired routing pattern FPGAs
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia...
FCCM
2005
IEEE
111views VLSI» more  FCCM 2005»
13 years 12 months ago
A High-Performance Asynchronous FPGA: Test Results
We report test results from a prototype asynchronous FPGA (AFPGA) implemented in TSMC’s 0.18μm CMOS process. The AFPGA uses SRAM-based configuration bits with pipelined logic ...
David Fang, John Teifel, Rajit Manohar
SLIP
2005
ACM
13 years 11 months ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...
ISCAS
2005
IEEE
131views Hardware» more  ISCAS 2005»
13 years 12 months ago
A low-complexity scanned-array 3D IIR frequency-planar filter
— We extend a 3D differential-operator-based filter architecture to a 3D IIR FPGA filter circuit implementation employing a recently proposed scanned-array method, which uses a s...
Arjuna Madanayake, Leonard T. Bruton