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104
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FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 3 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
122
Voted
FPL
2006
Springer
96views Hardware» more  FPL 2006»
15 years 3 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
133
Voted
FPL
2006
Springer
211views Hardware» more  FPL 2006»
15 years 3 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
GCCB
2006
15 years 3 months ago
Accelerated microRNA-Precursor Detection Using the Smith-Waterman Algorithm on FPGAs
During the last few years more and more functionalities of RNA have been discovered that were previously thought of being carried out by proteins alone. One of the most striking di...
Patrick May, Gunnar W. Klau, Markus Bauer, Thomas ...
108
Voted
DAGSTUHL
2006
15 years 1 months ago
Physical 2D Morphware and Power Reduction Methods for Everyone
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
Jürgen Becker, Michael Hübner, Katarina ...