Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-C...
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globa...
Julian J. H. Pontes, Rafael Soares, Ewerson Carval...