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ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
15 years 4 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
NOCS
2007
IEEE
15 years 4 months ago
NoC-Based FPGA: Architecture and Routing
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
Roman Gindin, Israel Cidon, Idit Keidar
FCCM
2007
IEEE
100views VLSI» more  FCCM 2007»
15 years 4 months ago
A Library and Platform for FPGA Bitstream Manipulation
— Since 1998, no commercially available FPGA has been accompanied by public documentation of its native machine code (or bitstream) format. Consequently, research in reconfigura...
Adam Megacz
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 2 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
15 years 11 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood