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BIOSYSTEMS
2007
92views more  BIOSYSTEMS 2007»
14 years 10 months ago
A phase-based stereo vision system-on-a-chip
A simple and fast technique for depth estimation based on phase measurement has been adopted for the implementation of a real-time stereo system with sub-pixel resolution on an FP...
Javier Díaz, Eduardo Ros, Silvio P. Sabatin...
VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
15 years 11 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
NOCS
2007
IEEE
15 years 4 months ago
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh a...
Zied Marrakchi, Hayder Mrabet, Christian Masson, H...
FPL
2007
Springer
106views Hardware» more  FPL 2007»
15 years 4 months ago
Monte Carlo Logarithmic Number System for Model Predictive Control
Simple algorithms can be analytically characterized, but such analysis is questionable or even impossible for more complicated algorithms, such as Model Predictive Control (MPC). ...
Panagiotis D. Vouzis, Sylvain Collange, Mark G. Ar...
CODES
2007
IEEE
15 years 4 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha