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109
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CSREAESA
2006
14 years 11 months ago
An Architecture for Fail-Silent Operation of FPGAs and Configurable SoCs
Lee Lerner, Charles E. Stroud
75
Voted
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
15 years 4 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan
70
Voted
ERSA
2007
142views Hardware» more  ERSA 2007»
14 years 11 months ago
An FPGA Implementation of Reciprocal Sums for SPME
Molecular Dynamics simulations have become an interesting target for acceleration using Field-Programmable Gate Arrays (FPGA). Still to be attempted completely in FPGA hardware is...
Sam Lee, Paul Chow
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
15 years 4 months ago
GlitchLess: an active glitch minimization technique for FPGAs
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
68
Voted
ERSA
2006
132views Hardware» more  ERSA 2006»
14 years 11 months ago
Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers
: A brief review of mapping generalized template matching operations onto reconfigurable computers is given. A combinatorial optimization process, where the objective is to minimiz...
Xuejun Liang, Qutaibah M. Malluhi