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ERSA
2006
114views Hardware» more  ERSA 2006»
14 years 11 months ago
Architectural Support for Runtime 2D Partial Reconfiguration
: Traditional FPGA architectures can potentially allow the dynamic swap in and out of hardware tasks through 2D partial reconfiguration. A segmented bus structure is proposed to be...
Fei Wang, Jack S. N. Jean
73
Voted
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 4 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
72
Voted
ICCD
2007
IEEE
245views Hardware» more  ICCD 2007»
15 years 7 months ago
FPGA global routing architecture optimization using a multicommodity flow approach
Low energy and small switch area usage are two of the important design objectives in FPGA global routing architecture design. This paper presents an improved MCF model based CAD ï...
Yuanfang Hu, Yi Zhu, Michael Bedford Taylor, Chung...
97
Voted
FPL
2007
Springer
154views Hardware» more  FPL 2007»
15 years 4 months ago
Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection
In recent years, IP protection of FPGA hardware designs has become a requirement for many IP vendors. To this end solutions have been proposed based on the idea of bitstream encry...
Jorge Guajardo, Sandeep Kumar, Geert Jan Schrijen,...
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
15 years 7 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...