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    TVLSI
    2008
    106views more  TVLSI 2008»
    New Non-Volatile Memory Structures for FPGA Architectures
    14 years 9 months ago
    New Non-Volatile Memory Structures for FPGA Architectures
    Download  www.ee.ucla.edu
    A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
    David Choi, Kyu Choi, John D. Villasenor
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    FPL
    2008
    Springer
    175views Hardware» more  FPL 2008»
    File system access from reconfigurable FPGA hardware processes in BORPH
    14 years 11 months ago
    File system access from reconfigurable FPGA hardware processes in BORPH
    Download  www.eee.hku.hk
    This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
    Hayden Kwok-Hay So, Robert W. Brodersen
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    BCS
    2008
    166views Computer Science» more  BCS 2008»
    Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation
    14 years 11 months ago
    Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation
    Download  cas.ee.ic.ac.uk
    This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally-intensive applications can be specified. Field-Pr...
    Qiang Liu, George A. Constantinides, Konstantinos ...
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    FPGA
    2008
    ACM
    184views FPGA» more  FPGA 2008»
    Mapping for better than worst-case delays in LUT-based FPGA designs
    14 years 11 months ago
    Mapping for better than worst-case delays in LUT-based FPGA designs
    Download  cadlab.cs.ucla.edu
    Current advances in chip design and manufacturing have allowed IC manufacturing to approach the nanometer range. As the feature size scales down, greater variability is experience...
    Kirill Minkovich, Jason Cong
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    DAC
    2008
    ACM
    145views Computer Architecture» more  DAC 2008»
    Enhancing timing-driven FPGA placement for pipelined netlists
    15 years 10 months ago
    Enhancing timing-driven FPGA placement for pipelined netlists
    Download  www.ee.washington.edu
    FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
    Kenneth Eguro, Scott Hauck
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