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FPGA
2008
ACM
131views FPGA» more  FPGA 2008»
14 years 11 months ago
WireMap: FPGA technology mapping for improved routability
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...
Stephen Jang, Billy Chan, Kevin Chung, Alan Mishch...
FPL
2008
Springer
112views Hardware» more  FPL 2008»
14 years 11 months ago
Secure FPGA configuration architecture preventing system downgrade
In the context of FPGAs, system downgrade consists in preventing the update of the hardware configuration or in replaying an old bitstream. The objective can be to preclude a syst...
Benoît Badrignans, Reouven Elbaz, Lionel Tor...
ISPDC
2008
IEEE
15 years 3 months ago
FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations
Multi–comparand associative processors are efficient in parallel processing of complex search problems that arise from many application areas including computational geometry, ...
Zbigniew Kokosinski, Bartlomiej Malus
76
Voted
ERSA
2008
185views Hardware» more  ERSA 2008»
14 years 11 months ago
Design Framework for Partial Run-Time FPGA Reconfiguration
Partial reconfiguration (PR) reveals many opportunities for integration into FPGA design for potential system optimizations such as reduced area, increased performance, and increa...
Chris Conger, Ann Gordon-Ross, Alan D. George
INTEGRATION
2007
98views more  INTEGRATION 2007»
14 years 9 months ago
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
The ubiquitous presence of mobile devices and the demand for better performance and efficiency have motivated research into embedded implementations of cryptography algorithms. I...
T. S. Ganesh, Michael T. Frederick, T. S. B. Sudar...