Sciweavers

259 search results - page 29 / 52
» fpga 2008
Sort
View
87
Voted
TVLSI
2008
149views more  TVLSI 2008»
14 years 9 months ago
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpo...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
TSP
2008
82views more  TSP 2008»
14 years 9 months ago
Fully Parallel Stochastic LDPC Decoders
Stochastic decoding is a new approach to iterative decoding on graphs. This paper presents a hardware architecture for fully parallel stochastic low-density parity-check (LDPC) dec...
Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gros...
CEE
2004
205views more  CEE 2004»
14 years 9 months ago
64-bit Block ciphers: hardware implementations and comparison analysis
A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are u...
Paris Kitsos, Nicolas Sklavos, Michalis D. Galanis...
FPL
2008
Springer
117views Hardware» more  FPL 2008»
14 years 11 months ago
A versatile hardware architecture for a CFAR detector based on a linear insertion sorter
This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detec...
Roberto Perez-Andrade, René Cumplido, Claud...
DSD
2008
IEEE
79views Hardware» more  DSD 2008»
15 years 4 months ago
Digital Systems Architectures Based on On-line Checkers
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
Martin Straka, Zdenek Kotásek, Jan Winter