This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...
A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at runtime is presented. Based on the network on chip (NoC) infrastructure...
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, J&...
Domain-specific heterogeneous reconfigurable arrays provide high performance over generic Field Programmable Gate Arrays (FPGAs) while maintaining the flexibility for that particu...
Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian ...
In this paper, we propose a placement method for islandstyle FPGAs, based on recursive bi-partitioning followed by application of space-filling curves. Experimental results of ou...
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...