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FPL
2005
Springer
114views Hardware» more  FPL 2005»
15 years 3 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...
65
Voted
FPL
2005
Springer
165views Hardware» more  FPL 2005»
15 years 3 months ago
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices
A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at runtime is presented. Based on the network on chip (NoC) infrastructure...
Christophe Bobda, Ali Ahmadinia, Mateusz Majer, J&...
FPL
2005
Springer
103views Hardware» more  FPL 2005»
15 years 3 months ago
Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications
Domain-specific heterogeneous reconfigurable arrays provide high performance over generic Field Programmable Gate Arrays (FPGAs) while maintaining the flexibility for that particu...
Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian ...
FPL
2005
Springer
127views Hardware» more  FPL 2005»
15 years 3 months ago
Fast FPGA Placement using Space-filling Curve
In this paper, we propose a placement method for islandstyle FPGAs, based on recursive bi-partitioning followed by application of space-filling curves. Experimental results of ou...
Pritha Banerjee, Subhasis Bhattacharjee, Susmita S...
79
Voted
FPL
2005
Springer
96views Hardware» more  FPL 2005»
15 years 3 months ago
Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs
Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a fu...
Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, ...