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FPL
2008
Springer
138views Hardware» more  FPL 2008»
14 years 11 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
FPL
2008
Springer
119views Hardware» more  FPL 2008»
14 years 11 months ago
Polymorphic wavelet architectures using reconfigurable hardware
Traditional microprocessor-based solutions are insufficient to serve the dynamic throughput demands of real-time scalable multimedia processing systems. This paper introduces a Po...
Amit Pande, Joseph Zambreno
FPL
2008
Springer
107views Hardware» more  FPL 2008»
14 years 11 months ago
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
FPL
2008
Springer
180views Hardware» more  FPL 2008»
14 years 11 months ago
Compiled hardware acceleration of Molecular Dynamics code
The objective of Molecular Dynamics (MD) simulations is to determine the shape of a molecule in a given biomolecular environment. These simulations are very demanding computationa...
Jason R. Villarreal, Walid A. Najjar
FPL
2008
Springer
154views Hardware» more  FPL 2008»
14 years 11 months ago
Numerical function generators using bilinear interpolation
Two-variable numerical functions are widely used in various applications, such as computer graphics and digital signal processing. Fast and compact hardware implementations are re...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler