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FPL
2008
Springer
92views Hardware» more  FPL 2008»
14 years 11 months ago
Parallel hardware objects for dynamically partial reconfiguration
Many of today's software-to-hardware compiler projects try to find dataflow parallelism in a sequential program description and use it to generate parallel running hardware c...
Norbert Abel, Frederik Grüll, Nick Meier, And...
FPL
2008
Springer
104views Hardware» more  FPL 2008»
14 years 11 months ago
A technique for minimizing power during FPGA placement
This paper considers the implementation of an annealing technique for dynamic power reduction in FPGAs. The proposed method comprises a power-aware objective function for placemen...
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Ya...
FPL
2008
Springer
141views Hardware» more  FPL 2008»
14 years 11 months ago
An analytical model describing the relationships between logic architecture and FPGA density
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the ...
Andrew Lam, Steven J. E. Wilton, Philip Heng Wai L...
FPL
2008
Springer
96views Hardware» more  FPL 2008»
14 years 11 months ago
Towards benchmarking energy efficiency of reconfigurable architectures
Energy research in reconfigurable architectures often involves legacy benchmarks such as the MCNC benchmarks. These benchmarks, however, are not well-suited for assessing energy c...
Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y....
FPL
2008
Springer
110views Hardware» more  FPL 2008»
14 years 11 months ago
Automatic generation of run-time parameterizable configurations
In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (Field Programmable Gate Arrays) can ...
Karel Bruneel, Dirk Stroobandt