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GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
15 years 1 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
15 years 1 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
15 years 1 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
GLVLSI
2009
IEEE
103views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Enhancing bug hunting using high-level symbolic simulation
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Ther...
Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui ...
GLVLSI
2009
IEEE
142views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Hardware-accelerated gradient noise for graphics
A synthetic noise function is a key component of most computer graphics rendering systems. This pseudo-random noise function is used to create a wide variety of natural looking te...
Josef B. Spjut, Andrew E. Kensler, Erik Brunvand