Sciweavers

31 search results - page 3 / 7
» glvlsi 2010
Sort
View
GLVLSI
2010
IEEE
119views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Line width optimization for interdigitated power/ground networks
Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with...
Renatas Jakushokas, Eby G. Friedman
GLVLSI
2010
IEEE
131views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Clock skew reduction by self-compensating manufacturing variability with on-chip sensors
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
Shinya Abe, Kenichi Shinkai, Masanori Hashimoto, T...
GLVLSI
2010
IEEE
178views VLSI» more  GLVLSI 2010»
15 years 2 months ago
Improving the testability and reliability of sequential circuits with invariant logic
In this paper, we investigate dual applications for logic implications, which can provide both online error detection capabilities and improve the testing efficiency of an integr...
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris...
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
14 years 12 months ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen
GLVLSI
2010
IEEE
141views VLSI» more  GLVLSI 2010»
14 years 10 months ago
Energy-efficient redundant execution for chip multiprocessors
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
Pramod Subramanyan, Virendra Singh, Kewal K. Saluj...