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GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
GLVLSI
2010
IEEE
190views VLSI» more  GLVLSI 2010»
14 years 12 months ago
A linear statistical analysis for full-chip leakage power with spatial correlation
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorith...
Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong
GLVLSI
2010
IEEE
171views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Timing-driven variation-aware nonuniform clock mesh synthesis
Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as ...
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby...
GLVLSI
2010
IEEE
172views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Online convex optimization-based algorithm for thermal management of MPSoCs
Meeting the temperature constraints and reducing the hot-spots are critical for achieving reliable and efficient operation of complex multi-core systems. The goal of thermal mana...
Francesco Zanini, David Atienza, Giovanni De Miche...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...