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HIPEAC
2010
Springer
15 years 2 months ago
2010
Springer
124
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HIPEAC
2010
Springer
15 years 9 months ago
2010
Springer
Abstract. Multi-core processors with shared last-level caches are vulnerable to performance inefficiencies and fairness issues when the cache is not carefully managed between the m...
81
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HIPEAC
2010
Springer
15 years 9 months ago
2010
Springer
We address the problem of performance and power-efficient thread allocation in a CMP. To that end, based on analytical model, we introduce a parameterized performance/power metric ...
98
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HIPEAC
2010
Springer
15 years 9 months ago
2010
Springer
Abstract. This paper presents remote store programming (RSP), a programming paradigm which combines usability and efficiency through the exploitation of a simple hardware mechanism...
135
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HIPEAC
2010
Springer
14 years 10 months ago
2010
Springer
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...