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90
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HPCA
1997
IEEE
15 years 4 months ago
Multiple Branch and Block Prediction
Steven Wallace, Nader Bagherzadeh
69
Voted
HPCA
1997
IEEE
15 years 5 months ago
Software DSM Protocols that Adapt between Single Writer and Multiple Writer
Cristiana Amza, Alan L. Cox, Sandhya Dwarkadas, Wi...
79
Voted
HPCA
1997
IEEE
15 years 4 months ago
Control Flow Speculation in Multiscalar Processors
Quinn Jacobson, Steve Bennett, Nikhil Sharma, Jame...
97
Voted
HPCA
1997
IEEE
15 years 5 months ago
Design Issues and Tradeoffs for Write Buffers
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
Kevin Skadron, Douglas W. Clark