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ICCAD
1994
IEEE
95views Hardware» more  ICCAD 1994»
13 years 10 months ago
Provably correct high-level timing analysis without path sensitization
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
ICCAD
1994
IEEE
61views Hardware» more  ICCAD 1994»
13 years 10 months ago
Simultaneous driver and wire sizing for performance and power optimization
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
Jason Cong, Cheng-Kok Koh
ICCAD
1994
IEEE
76views Hardware» more  ICCAD 1994»
13 years 10 months ago
An efficient procedure for the synthesis of fast self-testable controller structures
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
Sybille Hellebrand, Hans-Joachim Wunderlich
ICCAD
1994
IEEE
134views Hardware» more  ICCAD 1994»
13 years 10 months ago
Boolean constrained encoding: a new formulation and a case study
1 This paper provides a new, generalized approach to the problem of encoding information as vectors of binary digits. We furnish a formal definition for the Boolean constrained enc...
Ney Laert Vilar Calazans
ICCAD
1994
IEEE
105views Hardware» more  ICCAD 1994»
13 years 10 months ago
Register assignment through resource classification for ASIP microcode generation
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
Clifford Liem, Trevor C. May, Pierre G. Paulin