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98
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ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
15 years 6 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
15 years 6 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
95
Voted
ICCAD
1998
IEEE
71views Hardware» more  ICCAD 1998»
15 years 6 months ago
High-level variable selection for partial-scan implementation
In this paper, we propose a high-level variable selection for partial-scan approach to improve the testability of digital systems. The testability of a design is evaluated at the ...
Frank F. Hsu, Janak H. Patel
ICCAD
1998
IEEE
66views Hardware» more  ICCAD 1998»
15 years 6 months ago
Tight integration of combinational verification methods
Combinational verification is an important piece of most equivalence checking tools. In the recent past, many combinational verification algorithms have appeared in the literature...
Jerry R. Burch, Vigyan Singhal
ICCAD
1998
IEEE
98views Hardware» more  ICCAD 1998»
15 years 6 months ago
Determination of worst-case aggressor alignment for delay calculation
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...