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ICCAD
2000
IEEE
104views Hardware» more  ICCAD 2000»
15 years 2 months ago
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures
— Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cl...
Ian G. Harris, Russell Tessier
ICCAD
2000
IEEE
99views Hardware» more  ICCAD 2000»
15 years 2 months ago
On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools
The incremental, “construct by correction” design methodology has become widespread in constraint-dominated DSM design. We study the problem of ECO for physical design domains...
Andrew B. Kahng, Stefanus Mantik
ICCAD
2000
IEEE
73views Hardware» more  ICCAD 2000»
15 years 2 months ago
Simulation and Optimization of the Power Distribution Network in VLSI Circuits
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
ICCAD
2000
IEEE
109views Hardware» more  ICCAD 2000»
15 years 2 months ago
General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs
–An FPGA switch box is said to be hyper-universal if it is routable for all possible surrounding multi-pin net topologies satisfying the routing resource constraints. It is desir...
Hongbing Fan, Jiping Liu, Yu-Liang Wu
ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
15 years 2 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...