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ICCAD
2002
IEEE
107views Hardware» more  ICCAD 2002»
15 years 6 months ago
Characteristic faults and spectral information for logic BIST
We present a new method of built-in-self-test (BIST) for sequential circuits and system-on-a-chip (SOC) using characteristic faults and circuitspecific spectral information in th...
Xiaoding Chen, Michael S. Hsiao
ICCAD
2002
IEEE
149views Hardware» more  ICCAD 2002»
15 years 6 months ago
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
Hiran Tennakoon, Carl Sechen
ICCAD
2002
IEEE
126views Hardware» more  ICCAD 2002»
15 years 2 months ago
Robust and passive model order reduction for circuits containing susceptance elements
Numerous approaches have been proposed to address the overwhelming modeling problems that result from the emergence of magnetic coupling as a dominant performance factor for ICs a...
Hui Zheng, Lawrence T. Pileggi
ICCAD
2002
IEEE
129views Hardware» more  ICCAD 2002»
15 years 6 months ago
Transmission line design of clock trees
We investigate appropriate regimes for transmission line propagation of signals on digital integrated circuits. We start from exact solutions to the transmission line equations pr...
Rafael Escovar, Roberto Suaya
ICCAD
2002
IEEE
175views Hardware» more  ICCAD 2002»
15 years 6 months ago
Efficient model order reduction via multi-node moment matching
- The new concept of Multi-node Moment Matching (MMM) is introduced in this paper. The MMM technique simultaneously matches the moments at several nodes of a circuit using explicit...
Yehea I. Ismail