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ICCAD
2005
IEEE
110views Hardware» more  ICCAD 2005»
15 years 6 months ago
Computational geometry based placement migration
Placement migration is a critical step to address a variety of postplacement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To...
Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhi...
ICCAD
2005
IEEE
95views Hardware» more  ICCAD 2005»
15 years 6 months ago
Application-specific network-on-chip architecture customization via long-range link insertion
Networks-on-Chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either complete...
Ümit Y. Ogras, Radu Marculescu
ICCAD
2005
IEEE
168views Hardware» more  ICCAD 2005»
15 years 6 months ago
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
Jeng-Liang Tsai, Lizheng Zhang
ICCAD
2005
IEEE
120views Hardware» more  ICCAD 2005»
15 years 6 months ago
Practical techniques to reduce skew and its variations in buffered clock networks
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, P...
ICCAD
2005
IEEE
90views Hardware» more  ICCAD 2005»
15 years 6 months ago
Scalable compositional minimization via static analysis
State-equivalence based reduction techniques, e.g. bisimulation minimization, can be used to reduce a state transition system to facilitate subsequent verification tasks. However...
Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz