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ICCD
2004
IEEE
15 years 7 months ago
2004
IEEE
We selectively generate and optimize the frames constructed by the rePLay architecture statically. Since static analysis provides a global view of the interaction between the basi...
ICCD
2004
IEEE
15 years 7 months ago
2004
IEEE
— With power a major limiting factor in the design of scalable interconnected systems, power-aware networks will become inherent components of single-chip and multi-chip systems....
ICCD
2004
IEEE
15 years 7 months ago
2004
IEEE
In modern technologies, process variations can be quite substantial, often causing design timing failures. It is essential that those errors be correctly and quickly diagnosed. In...
ICCD
2004
IEEE
15 years 7 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
ICCD
2004
IEEE
15 years 7 months ago
2004
IEEE
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...