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ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
15 years 6 months ago
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug
Abstract— This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradig...
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
15 years 6 months ago
Design and Implementation of Software Objects in Hardware
This paper proposes a novel approach to implement software object in hardware. Data-Memory mapping schemes are investigated and four hardware object design schemes are proposed an...
Fu-Chiung Cheng, Hung-Chi Wu
ICCD
2006
IEEE
119views Hardware» more  ICCD 2006»
15 years 6 months ago
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling
— This paper presents a framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced...
Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. I...
ICCD
2006
IEEE
125views Hardware» more  ICCD 2006»
15 years 6 months ago
Partial Functional Manipulation Based Wirelength Minimization
—In-place flipping of rectangular blocks/cells can potentially reduce the wirelength of a floorplan/placement solution without changing the chip area, In a recent work [Hao 05], ...
Avijit Dutta, David Z. Pan
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
15 years 6 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...