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ICPP
2008
IEEE
15 years 4 months ago
Implementing and Exploiting Inevitability in Software Transactional Memory
—Transactional Memory (TM) takes responsibility for concurrent, atomic execution of labeled regions of code, freeing the programmer from the need to manage locks. Typical impleme...
Michael F. Spear, Michael Silverman, Luke Dalessan...
101
Voted
ICPP
2008
IEEE
15 years 4 months ago
Thermal Management for 3D Processors via Task Scheduling
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
Xiuyi Zhou, Yi Xu, Yu Du, Youtao Zhang, Jun Yang 0...
92
Voted
ICPP
2008
IEEE
15 years 4 months ago
Solving Large, Irregular Graph Problems Using Adaptive Work-Stealing
Solving large, irregular graph problems efficiently is challenging. Current software systems and commodity multiprocessors do not support fine-grained, irregular parallelism wel...
Guojing Cong, Sreedhar B. Kodali, Sriram Krishnamo...
ICPP
2008
IEEE
15 years 4 months ago
Improving the Performance of Multithreaded Sparse Matrix-Vector Multiplication Using Index and Value Compression
Abstract—The Sparse Matrix-Vector Multiplication kernel exhibits limited potential for taking advantage of modern shared memory architectures due to its large memory bandwidth re...
Kornilios Kourtis, Georgios I. Goumas, Nectarios K...
99
Voted
ICPP
2008
IEEE
15 years 4 months ago
VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
Heiner Litz, Holger Fröning, Mondrian Nü...