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IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
We discuss the design of a novel analog checker that monitors two duplicate signals and provides a digital error indication when their absolute difference is unacceptably large. Th...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper we present a technique which allows to reduce the crosstalk-induced delay within busses implementing an error detecting/correcting code. This technique is based on t...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...