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81
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APSEC
2000
IEEE
15 years 5 months ago
Building Formal Models for Software Requirements
Axel van Lamsweerde
73
Voted
ASYNC
2000
IEEE
87views Hardware» more  ASYNC 2000»
15 years 5 months ago
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
Ivan Blunno, Luciano Lavagno
90
Voted
ASYNC
2000
IEEE
94views Hardware» more  ASYNC 2000»
15 years 5 months ago
Formal Verification of Safety Properties in Timed Circuits
Marco A. Peña, Jordi Cortadella, Enric Past...
ATS
2000
IEEE
59views Hardware» more  ATS 2000»
15 years 5 months ago
Testing in the Fourth Dimension
Vishwani D. Agrawal, Kwang-Ting Cheng