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ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
A memory model for a shared memory, multiprocessor commonly and often implicitly assumed by programmers is that of sequential consistency. This model guarantees that all memory ac...
ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
Indirect branch prediction is likely to become increasingly important in the future because indirect branches occur more frequently in object-oriented programs. With misprediction ...
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ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...
ISCA
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths ...