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ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
15 years 2 months ago
Using Prediction to Accelerate Coherence Protocols
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
Shubhendu S. Mukherjee, Mark D. Hill
ISCA
1998
IEEE
144views Hardware» more  ISCA 1998»
15 years 2 months ago
Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism
This paper investigates the placement of data and parity on redundant disk arrays. Declustered organizations have been traditionally used to achieve fast reconstruction of a faile...
Guillermo A. Alvarez, Walter A. Burkhard, Larry J....
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 2 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
ISCA
1998
IEEE
118views Hardware» more  ISCA 1998»
15 years 2 months ago
Active Messages: A Mechanism for Integrated Communication and Computation
The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without ...
Thorsten von Eicken, David E. Culler, Seth Copen G...
ISCA
1998
IEEE
142views Hardware» more  ISCA 1998»
15 years 2 months ago
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work
Pipeline flushes due to branch mispredictions is one of the most serious problems facing the designer of a deeply pipelined, superscalar processor. Many branch predictors have bee...
Marius Evers, Sanjay J. Patel, Robert S. Chappell,...