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ICCAD
1998
IEEE
116views Hardware» more  ICCAD 1998»
15 years 2 months ago
On primitive fault test generation in non-scan sequential circuits
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
Ramesh C. Tekumalla, Premachandran R. Menon
IPPS
1998
IEEE
15 years 2 months ago
Meta-heuristics for Circuit Partitioning in Parallel Test Generation
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
Consolación Gil, Julio Ortega, Antonio F. D...
ISPD
1998
ACM
91views Hardware» more  ISPD 1998»
15 years 2 months ago
Estimation of maximum current envelope for power bus analysis and design
In this paper we present an input pattern independent method to compute the maximum current envelope, which is an upper bound over all possible current waveforms drawn by a circui...
Sudhakar Bobba, Ibrahim N. Hajj
VTS
1998
IEEE
124views Hardware» more  VTS 1998»
15 years 2 months ago
A Test Pattern Generation Methodology for Low-Power Consumption
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
FTCS
1993
94views more  FTCS 1993»
14 years 11 months ago
Balance Testing of Logic Circuits
We present a new test response compression method called cumulative balance testing (CBT)that extends both balance testing and accumulatorcompression testing. CBT uses an accumulat...
Krishnendu Chakrabarty, John P. Hayes