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ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
15 years 4 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
15 years 4 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
ISCA
2007
IEEE
103views Hardware» more  ISCA 2007»
15 years 4 months ago
Ginger: control independence using tag rewriting
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
Andrew D. Hilton, Amir Roth
ISCA
2006
IEEE
182views Hardware» more  ISCA 2006»
15 years 3 months ago
Cooperative Caching for Chip Multiprocessors
This paper presents CMP Cooperative Caching, a unified framework to manage a CMP’s aggregate on-chip cache resources. Cooperative caching combines the strengths of private and ...
Jichuan Chang, Gurindar S. Sohi
ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
15 years 3 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...