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ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 2 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the ā€œ3-Dā€ structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
15 years 2 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ISCA
2002
IEEE
123views Hardware» more  ISCA 2002»
15 years 2 months ago
Going the Distance for TLB Prefetching: An Application-Driven Study
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
Gokul B. Kandiraju, Anand Sivasubramaniam
ISCA
2011
IEEE
225views Hardware» more  ISCA 2011»
14 years 1 months ago
FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes
Blocked-execution multiprocessor architectures continuously run atomic blocks of instructions — also called Chunks. Such architectures can boost both performance and software pr...
Rishi Agarwal, Josep Torrellas
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 4 months ago
Automated design of application specific superscalar processors: an analytical approach
Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design sp...
Tejas Karkhanis, James E. Smith