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ISCA
2006
IEEE
138views Hardware» more  ISCA 2006»
15 years 3 months ago
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs
We present Program Demultiplexing (PD), an execution paradigm that creates concurrency in sequential programs by "demultiplexing" methods (functions or subroutines). Cal...
Saisanthosh Balakrishnan, Gurindar S. Sohi
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
15 years 3 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
15 years 3 months ago
Improving Cost, Performance, and Security of Memory Encryption and Authentication
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
Chenyu Yan, Daniel Englender, Milos Prvulovic, Bri...
ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
15 years 2 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 2 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...