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ISCAS
2007
IEEE
135views Hardware» more  ISCAS 2007»
15 years 3 months ago
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology
Abstract—In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to support a higher operating speed under a lower power supply (1xVDD). However, the...
Ming-Dou Ker, Hung-Tai Liao
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
15 years 3 months ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
ISCAS
2007
IEEE
120views Hardware» more  ISCAS 2007»
15 years 3 months ago
Clock Gating and Negative Edge Triggering for Energy Recovery Clock
Energy recovery clocking has been demonstrated as an effective method for reducing the clock power. In this method the conventional square wave clock signal is replaced by a sinus...
Vishwanadh Tirumalashetty, Hamid Mahmoodi
ISCAS
2007
IEEE
124views Hardware» more  ISCAS 2007»
15 years 3 months ago
CMOS Current-controlled Oscillators
— The work presented in this paper is about the design of current-controlled oscillators (ICO). Two ICOs are proposed. Aiming at reducing the duration of the short-circuit curren...
Junhong Zhao, Chunyan Wang
ISCAS
2007
IEEE
107views Hardware» more  ISCAS 2007»
15 years 3 months ago
Architecture Level Power-Performance Tradeoffs for Pipelined Designs
Abstract—This paper presents a method to investigate powerperformance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It w...
Haider Ali, Bashir M. Al-Hashimi